CMOS circuits are used in a variety of integrated circuit (IC) applications. A CMOS process can be used to fabricate many different sorts of functionality, such as memory, logic, and switching, and thus CMOS techniques are particularly desirable in applications where an IC includes several different types of functional blocks.
One family of ICs employing CMOS fabrication techniques are programmable logic devices (PLDs). PLDs are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more function blocks connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms PLD and programmable logic device include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
Power consumption of an IC generally increases with increasing complexity (e.g., number of devices or gates) for a given fabrication technology (e.g., CMOS node spacing). In some applications, a PLD has resources that are not required for an application (i.e., in the configured PLD or other IC). For example, the application uses a portion, but not all, of the logic resources of the PLD, leaving some logic blocks unused. An unused block might still consume power, such as leakage current. De-powering unused resources of an IC conserves power and reduces the operating temperature of the IC, both of which are typically desirable.
Various techniques have been developed to conserve power in regions of an IC that are not used in a particular application. One technique is to back-bias unused regions to reduce leakage current; however, this typically uses an additional power supply for the IC. Another approach uses a switch to selectively power or depower a selected region (block) of an IC. Such a switch is often referred to as a power gate. A power gate should be of sufficiently low resistance so as to not consume significant power, significantly reduce the voltage through the device, or generate significant heat if the associated block is turned on (i.e., the power for the block flows through the power gate). This typically results in a physically large device, and a trade-off between the size of the power gate device and the acceptable degradation of performance is usually struck.
Techniques for selectively de-powering regions of an IC that avoid the disadvantages of the prior art are desirable.